Semiconductor devices are fabricated by sequentially depositing insulating (dielectric) layers, conductive layers and semiconductor layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon. A common conductive material used in the past for conductive lines was aluminum, which can be directly etched. However, as performance demands of integrated circuits (“ICs”) continued, aluminum was lacking both because its resistivity became unacceptable, and the challenge of making smaller, reliable interconnects with aluminum.
Accordingly, aluminum interconnects were replaced with the lower resistivity copper. In contrast to aluminum, copper interconnects are made by a metal polishing process (dual damascene) rather than direct etching because (1) of copper corrosion during the etch process, and (2) the challenge of overlay of separate via, line lithography steps. However, as dimensions continue to shrink, especially as the 7 nm node approaches, filling aggressive dual damascene openings and the liner occupying much of the interconnect space compels a search for alternative methods of making interconnects.